1. Field of the Invention
The invention relates to a method for verifying a resistive memory and a verifying circuit for a resistive memory. Particularly, the invention relates to the method for writing and verifying the resistive memory by using a bit line voltage, and the bit line voltage continuously increases or decreases during a writing and verifying timing period.
2. Description of Related Art
Based on the demand for next-generation non-volatile memory, a kind of resistive random access memory (RRAM) have been developed. For getting the RRAM with better uniformity, a verifying operation with a good performance on the RRAM is necessary.
Referring to FIG. 1, FIG. 1 illustrates a waveform plot for setting the RRAM in conventional art. During a writing and verifying timing period TV, a word line signal WL is enabled (pulled to high voltage level), and a bit line voltage VVER is applied on a bit line of a selected resistive memory cell of the RRAM, and voltage level of the bit line voltage VVER is held on a constant voltage level during the writing and verifying timing period TV. In the conventional art, a bit line current CBL is detected during the writing and verifying timing period TV. By comparing the bit line current CBL with a target bit line current, whether the writing operation of the RRAM is finished or not can be determined. If the bit line current CBL does not reach to the target bit line current, the selected resistive memory cell should be set once more. If the bit line current CBL reaches to the target bit line current, the writing operation (set operation) on the selected resistive memory cell is completed.
That is, when the bit line voltage VVER is not well defined, the cycles of the writing and verifying timing period TV is hard to be controlled. Further, since the bias voltage for bit line voltage VVER is constant and the resistance is varied during the writing operation, the time of the writing operation may be too large. The performance of the writing operation for the RRAM is reduced.